PIC16F722-I/SO MICROCHIP

Product Highlights

• Harvard architecture memory system with 16-Kbyte instruction cache and 8-Kbyte data cache.
• Two, 2-Kbyte on-chip SRAMs.
• Integer/fractional multiply-accumulate (MAC) unit.
• Divide unit.
• System debug interface.

Product Highlights

• Advanced RISC architecture ? On-chip 2-cycle multiplier
• High endurance, non-volatile memory segments
• JTAG (IEEE 1149.1 compliant) interface
• Peripheral features ? Real-time counter with separate oscillator
• Power-on reset (POR) and programmable brown-out detection
• Internal Calibrated RC oscillator
• External and internal interrupt sources
• Six sleep modes ? Idle, ADC noise reduction, power-save, power-down, standby and extended standby
• 32 Programmable I/O lines