The chip is based on the advanced RISC architecture, with an optional boot code section with independent lock bits. The chip features 32 ? 8 general-purpose working registers, an on-chip 2-cycle multiplier, 4Kbytes EEPROM, 8Kbytes internal SRAM, up-to 10,000 write/erase cycles on flash and 100,000 write/erase cycles on EEPROM.
Features:
- Advanced RISC Architecture
- High Endurance Non-volatile Memory Segments
- Q Touch Library Support
- JTAG (IEEE std. 1149.1 compliant) Interface
- Ultra-Low Power Consumption
- Special Microcontroller Features Like Power-on Reset and Programmable Brown-out Detection and Internal Calibrated Oscillator.
